Modern electronic systems include volatile or non-volatile memory that is used to store code or application data processed by application software. Recent developments of flash non-volatile memory (Flash) and dynamic random access memory (DRAM) have reduced data corruption, such that data reliability is very high and in most cases data is read out of these devices assuming no corruption. Even with these memory types, a status register in the memory may carry information about any data read failures that do occur. However, a host usually does not read the status after every data access due to additional communication time overhead in the system that would reduce system performance.
Corruption in the data read at the peripheral may result in erroneous code or data transmission to a processing device, e.g., a central processing unit (CPU) or the like. Processing erroneous code or data in turn can lead to system failures, which are hard to detect. And, recovery from system failure is very time consuming. For example, if a memory is used in a network, this system failure could cause significant down time, which is not acceptable in many systems. Such systems need immediate notification of any detected read error and provide a signal separate from the memory read data to indicate to the host that a read error has occurred.
Many systems also transfer data at high speeds, such that the period of time during which each bit of data is valid is very short, making it difficult for the host to know the optimal point in time to capture valid data. These systems often include a signal separate from the data to indicate the optimal point in time to capture valid data. This signal is often referred to as a receive data clock (RDC), a data-in-out strobe (DQS), or read data strobe (RDS). While the RDS provides an indication of the best point within a clock cycle to capture data, the RDS is expected to transition between signal levels within a fixed number of clocks following the beginning of a read access and to continue regular transitions during any set of sequential read accesses.